The present invention relates to testing of semiconductor devices, and more particularly, to a method of thermally stressing a semiconductor device and/or testing such semiconductor device at an elevated temperature.
P-type conductivity field effect transistors (“PFETs”) tend to suffer from negative bias temperature instability (“NBTI”), an effect which increases over the lifetime of the transistor with the amount of use of the transistor. The effect is usually more pronounced when the transistor operates is used at an elevated temperature for a large amount of time. NBTI results in a decrease in the threshold voltage and drive current of a PFET with use over time, making the PFET more difficult to turn on. Conversely, a “positive” bias temperature instability (“PBTI”) effect occurs in n-type FETs (“NFETs”), which are operated at an elevated temperature for a large amount of time. PBTI results in a long-term rise in the threshold voltage of the NFET, making the NFET more difficult to turn on.
NBTI is of particular concern for PFETs which are designed to operate at relatively low voltages, e.g., voltages of 1.2 V or less. Shifts in the threshold voltage and drive current of such PFETs have a significant impact upon performance. NBTI and PBTI are particularly pronounced in PFETs and NFETs, respectively, which have insulated gates, thin gate dielectrics and/or short channel lengths.
One goal of engineering is to “build” sufficient reliability into a transistor by performing accelerated lifetime stressing to reproduce how the transistor undergoes wearout over time. The design of the transistor can then be adjusted until the transistor is assured to degrade satisfactorily in the lifetime of the product. Heretofore, accelerated stressing techniques have been less than desirable for determining the long-term effects of NBTI. One requirement of accelerated lifetime stressing is to reproduce the results of wearout on a transistor in a relatively short period of time, while producing little or no disturbance to the device when tested.
In some stress/testing techniques, it is desirable to perform this characterization at the “wafer-level,” i.e., under conditions in which a chip which contains the transistor remains connected to one or more other chips of a wafer. Some such testing may also be performed “in-line,” i.e., at a time between performing other steps in a process of fabricating chips of a wafer. Such testing may involve application of stress test conditions to a device and monitoring for the effects of such test conditions upon the operation of the device. In order to justify such testing as a part of an in-line monitoring scheme, such stress test conditions and monitoring may need to be completed in a short period of time, for example, in about 10 seconds or less.
Another requirement of such testing is the ability to quickly elevate the temperature of a device of a wafer under test to a desired level for in-line testing. The ability to quickly achieve a desired elevated temperature for such in-line testing is a critical need for the continued development of complementary metal oxide semiconductor (“CMOS”) technology and monitoring of the fabrication process thereof. Monitoring techniques according to the prior art can only be applied at in-line test temperatures between 25 and 85 degrees Celsius. Such techniques are unable to monitor wearout mechanisms which are active at temperatures higher than 85 degrees Celsius. A particular constraint of such prior art techniques is long tester time, typically between 20 and 30 minutes, that is needed to increase the temperature of a transistor under test from that of an in-line testing temperature to a stress temperature of interest, which can be 140 degrees Celsius or higher. This long delay slows down the testing and monitoring process.
Reliability degradation mechanisms such as NBTI for PFET devices and PBTI for NFET devices, need sufficient high temperatures to become active; i.e., temperatures of at least about 100 degrees Celsius. To monitor the sensitivity of a FET to the manufacturing process, the channel of an FET must be heated quickly to a stress temperature needed to reproduce an equivalent amount of degradation that would be produced during the long lifetime of the FET. The inventors know of no effective inline monitor for NBTI that adequately addresses such need.
Resistive heaters which include a polysilicon element (“poly-heaters”) have been used to heat an FET when a current and voltages are applied to operate the FET. However, heretofore, such poly-heaters have not been able to raise the FET to a stress temperature fast enough to function as an inline monitor for NBTI or PBTI. One reason for this is the high thermal conductivity of silicon, which allows most of the heat generated by such poly-heaters to escape into an n-well of the device or deeper into a bulk region of the substrate. Poly-heaters are capable of imparting only a limited amount of heat to an FET.
Consequently an improved structure and method for heating the channel region of an FET are desired.